As is known, row decoders provide for addressing individual rows in a memory array according to the coded address with which they are supplied. The basic scheme of row decoders may be represented by a number of inverters (one for each row) controlled by a combinatorial circuit, which receives the input addresses and drives the inverters so that only one of them at a time presents a high output. More specifically, the combinatorial circuit provides for supplying a low logic signal to the inverter connected to the selected row (so that the inverter presents a high output) and a high logic signal to all the others. One such inverter is shown in FIG. 1, which shows an inverter 1 comprising a PMOS pull-up transistor 2 and an NMOS pull-down transistor 3 with the gate terminals connected to each other (node 4), the drain terminals connected to each other (output node 5), and the source terminals connected respectively to supply line 6 and ground.
The simplified arrangement described above operates correctly in read mode, wherein both the combinatorial circuit and the inverters present read voltage V.sub.cc as the high logic level, but not in programming mode, in which case, the combinatorial circuit supplies read voltage V.sub.cc as the high logic level at input 4 of the nonselected-row inverters, whereas supply line 6 is at programming voltage V.sub.pp &gt;V.sub.cc. As such, a voltage drop of other than zero exists between the gate and source terminals of pull-up transistors 2 of inverters 1, and, if this reaches the threshold value (threshold voltage) of transistors 2, these are turned on, and outputs 5 of the inverters are prevented from reaching the zero voltage value required to prevent stressing the connected cells and to ensure a correct logic level at the output.
One possible solution to the problem is to use a positive-feedback inverter with a PMOS feedback transistor connected between line 6 and input 4, and with the gate terminal connected to output 5.
As such, when the voltage at output 5 falls, the feedback transistor is turned on and connects node 4 to the programming voltage V.sub.pp of line 6, thus ensuring complete turn-off of pull-up transistor 2 and a zero output voltage.
The above solution, however, also presents drawbacks of its own. In the first place, layout problems arise owing to the output of the inverter having to be fed back, and solving the problem by driving the feedback transistor with a separate signal in turn creates problems in terms of synchronization. Secondly, problems arise as regards direct biasing of the drain-bulk junction of the PMOS transistors of NAND gate 10, which would have the source and bulk regions biased at V.sub.cc and the drain regions (connected to the output) biased at V.sub.pp. One possible solution to the problem is to provide an NMOS pass transistor or CMOS pass switch to separate the low-voltage (predecoding) portion from the high-voltage (actual decoding) portion.
Such a solution is shown in FIG. 2 wherein a three-input NAND gate 10, supplied at read voltage V.sub.cc and forming part of the combinatorial circuit for selecting the row, drives inverter 1 via an NMOS pass transistor 13 with the gate terminal biased at V.sub.cc ; and output node 5 is connected to the gate terminal of a PMOS feedback transistor 11 with the source terminal connected to line 6 and the drain terminal connected to node 4.
In the FIG. 2 solution, when the output of NAND gate 10 is high (V.sub.cc), pass transistor 13 operates as a diode by presenting two terminals (the gate terminal and the terminal connected to the output of NAND gate 10) at the same voltage, and therefore causes, between the output of NAND gate 10 and node 4, a voltage drop equal to its threshold voltage.
In addition to further complicating the circuitry, the FIG. 2 solution is therefore also unsatisfactory in the presence of low supply voltage, in which case, the voltage drop across pass transistor 13 prevents node 4 from reaching the high voltage required to ensure pull-up transistors 2 are turned off completely.
Moreover, besides merely shifting the problem of undesired biasing to other parts of the circuit, a CMOS pass switch is too bulky to be accommodated in the decoding stage, which is formed within the spacing between the array rows.